1. Technical Field
The present invention generally relates to contact formation for semiconductor devices. More particularly, the present invention relates to the inclusion of a barrier between different types of epitaxy to prevent merger thereof.
2. Background Information
The continued size reduction of semiconductor devices has consequences not only for the devices themselves (developing new fabrication techniques), but also for the metallization providing electrical connections to the devices. For example, with respect to three-dimensional transistors (e.g., FinFETs), conventional contact formation can easily result in a short between the gate contact and the source or drain contact unless the source/drain contact fully encompasses or “straps” all the fins. To avoid this prospect, conventional fabrication moves the gate contact farther away from its ideal location. In addition, as the space between different devices becomes smaller and smaller, a source/drain epi-to-epi short among different devices easily results.
Thus, a need exists for a way to prevent the source/drain epitaxy on different devices from shorting each other, and to keep the gate contact closer to the gate, while still avoiding a short between the gate contact and source/drain contact.